1. Field of the Invention
The present invention generally relates to data reproduction devices, and more particularly to a data reproduction device that can correct an optimum clock signal for sampling a reproduced signal.
2. Description of the Related Art
Data reproduction devices are widely used in data transmitting and receiving apparatuses for mobile phone or satellite communication and data recording and reproduction apparatuses for optical or magnetic disks. These devices are necessary for storing and transferring at high speed a large amount and a variety of information such as images and music.
In order to convert reproduced data into binary information data in a data reproduction apparatus such as a conventional optical or magnetic disk unit, first, it is necessary to reproduce a synchronization signal that indicates the start of the recorded data. The synchronization signal is reproduced using a phase-locked loop (PLL) circuit. The basic principle of the PLL is as follows. In the PLL, a voltage-controlled oscillator (VCO) generates a reference clock signal for digitizing a reproduced signal. Then, the phase of the clock signal and the phase of the reproduced signal are compared, and the phase of the clock signal is controlled so that a predetermined relationship is established between the phases of the clock signal and the reproduced signal.
FIG. 1 is a block diagram showing a data reproduction apparatus for optical disks including a conventional analog PLL for generating a clock signal synchronized with a reproduced signal. The data reproduction apparatus of FIG. 1 includes an optical head 102, an automatic gain control (AGC) and equalizer part 103, a conventional analog PLL 104, and a demodulator 120. The optical head 102 emits light to an optical disk 101 such as a magneto-optical disk, and converts the reflected light therefrom into an electrical signal. The AGC and equalizer part 103 receives the output signal of the optical head 102. The demodulator 120 demodulates the data reproduced by the PLL 104.
Further, the conventional analog PLL 104 includes an analog filter 105, an analog-to-digital (A/D) converter 106, a digital waveform equalizer (EQ) 107, a symbol determiner 108, a phase error detector 109, a digital-to-analog (D/A) converter 110, a loop filter 111, and a VCO 112.
Referring to FIG. 1, in the conventional analog PLL 104, the A/D converter 106 samples a reproduced signal 130 that has passed the analog filter 105 based on a clock signal output from the VCO 112. The reproduced signal 130 sampled by the A/D converter 106 is subjected to waveform equalization in the digital waveform equalizer 107. Then, the symbol determiner 108 determines the symbol of the reproduced signal 130. Next, the phase error detector 109 detects the phase error between the clock signal generated by the VCO 112 and the reproduced signal 130. Then, the D/A converter 110 converts the detected phase error to an analog phase error signal. Next, the oscillation clock frequency of the VCO 112 is controlled based on the analog phase error signal that has passed the loop filter 111. Thus, the output clock signal of the VCO 112 is controlled, while the A/D converter 106 again samples the reproduced signal 130 based on the output clock signal of the VCO 112. Through the repetition of this operation, the clock signal generated by the VCO 112 can gradually synchronize with the reproduced signal 130.
Next, FIG. 2 is a block diagram showing a data reproduction apparatus for optical disks including a conventional analog PLL employing a technique of using an external clock signal for synchronization (an external clock technique). In FIG. 2, the same elements as those of FIG. 1 are referred to by the same numerals. The data reproduction apparatus of FIG. 2 includes a conventional analog PLL 201 employing an external clock technique. The conventional analog PLL 201 includes the analog filter 105, the A/D converter 106, the digital waveform equalizer 107, the symbol determiner 108, the phase error detector 109, a fine clock mark (FCM) detector circuit 202, a PLL 203, and a delay circuit 204.
In contrast to the above-described self-clock technique employed for clock generation in the data reproduction apparatus of FIG. 1, which technique generates a clock signal for data reproduction from the reproduced signal of information data itself, the external clock technique generates a clock signal for data reproduction by synchronizing a PLL with the signal reproduced from special clock marks (FCM) embedded in the medium. In the configuration of FIG. 2, the FCM detector circuit 202 detects a clock mark reproduced signal 210. Then, the PLL 203 generates a clock signal that synchronizes with the FCM reproduced signal 210 detected by the FCM detector circuit 202.
According to the above-described external clock technique, the frequency information of the clock signal for data reproduction is obtainable using the clock marks as described above. Accordingly, there is the necessity of adjusting the phase error between the clock signal for data reproduction and the reproduced signal 130 which phase error results from the difference between a detection system for detecting the clock marks and a detection system for detecting the reproduced signal 130. In the configuration of FIG. 2, the delay circuit 204 adjusts this phase error.
In order to carry out the adjustment of this phase error in the configuration of FIG. 2, the delay circuit 204 delays the phase of the synchronizing clock signal based on the phase error obtained by the phase error detector 109, and supplies the phase-delayed clock signal to the A/D converter 106, which samples the reproduced signal 130 based on the supplied phase-delayed clock signal.
However, the above-described prior art has the following disadvantages.
Each of the above-described self-clock and external clock techniques requires a feedback loop. This makes it difficult to increase the speed of the clock signal for data reproduction at which speed the clock signal follows a variation in the reproduced signal 130. This also makes it difficult to increase data transfer rate. Further, there is a problem in that when the signal-to-noise (S/N) ratio is low, the deterioration of symbol determination error rate significantly affects the accuracy of phase adjustment and consequently prevents stable phase synchronization from being achieved.
Due to advanced data signal processing techniques such as the partial response maximum likelihood (PRML) technique, demodulation is now performable even at low S/N ratios. However, a decrease in the S/N ratio and an increase in the data transfer rate have made it difficult for the above-described prior-art PLLs to adjust the phase error between the clock signal for data reproduction and the reproduced signal with high accuracy. Further, a delay in the follow-up operation of the prior-art PLLs as well as the oscillation thereof due to the feedback loop have also made it difficult for the prior-art PLLs to correct the phase error at high speed.
Particularly in the case of applying an encoding/decoding technique called Turbo Coding, which has been recently proposed and employed in the field of telecommunications, to a data storage device, a higher recording density may be achieved than with the PRML technique. On the other hand, however, it has also become difficult, at the low S/N ratios resulting from the higher recording density, to synchronize the phases of the clock signal for data reproduction and the reproduced signal, and accurately detect an information data start mark (such as a synchronization signal) indicating the start of an information data region.